1. Field of the Invention
The present invention relates to solid-state image sensors and specifically to a class of CMOS image sensors with multiple charge detection nodes placed at various depths in the substrate to selectively detect light of different wavelengths. Sensors that use such pixels do not require wavelength selective filters to detect colors, and thus do not sacrifice Quantum Efficiency (QE) and resolution.
2. Description of the Related Art Including Information Disclosed Under 37 CFR 1.97 and 1.98
A typical image sensor detects light by converting impinging photons into electrons that are integrated (collected) in pixels of the image sensing area. After completing integration, collected charge is converted into a voltage using a suitable charge-to-voltage conversion structure. The sensed voltage is then supplied through various addressing circuitry and buffering amplifiers to the output terminals of the sensor. Placing various wavelength selective filters on top of the pixels allows only a chosen portion of the light spectrum to enter the pixel and generate charge. The description of the conventional concept of color sensing may be found for example in U.S. Pat. No. 4,845,548 to Kohno. However, this concept reduces detected light levels as well as array resolution, since a single pixel can sense only one color while rejecting other colors. Recently a new class of devices has been developed, called VERTICOLOR Image Sensors, as described for example in U.S. No. Pat. No. 6,727,521 to Merrill. These devices use a pixel structure with multiple vertically stacked charge detection nodes that detect color by measuring charge generated at different depths within the pixel. Since light of different wavelengths penetrates to different depths in the substrate, color is sensed directly within one pixel without the necessity of surface wavelength selective filters. This is one advantage of the VERTICOLOR concept and technology. One problem with placing multiple charge detection nodes vertically within a pixel is the large capacitance associated with each charge detection node that reduces the node conversion gain and thus the sensor sensitivity.
FIG. 1 illustrates a simplified cross section of pixel 100, which is from a prior art CMOS image sensor. On p+ type doped silicon substrate 101 there is p type doped region 102, which may be epitaxially grown, that extends all the way to the surface. P type doped region 102 contains vertically stacked n type doped layers 103, 104 and 105. These layers can be formed, for example, by ion implantation between consecutive epitaxial growth steps, or by other means. Various techniques are well known to those skilled in the art of modern silicon device fabrication processing technology and the descriptions here in are not meant to be limiting.
Similarly, n+ type doped vertical extensions (plugs) 106, 107, and 108 may be formed by ion implantation between epitaxial growth steps and serve as conductive connections that enable biasing and collection of photo-generated electrons in doped layers 103, 104 and 105 from the surface of the silicon substrate.
Plugs 106, 107 and 108 are contacted by metal regions 111, 112, and 113, which can be formed through holes in silicon-dioxide dielectric layer 110 or as multilevel interconnects over many types of dielectric layers, as is also well know in the art. Metal regions 111, 112, and 113 can be formed by a single metal, such as aluminum, or composed of complex metallization systems formed by various layers of titanium-nitride, titanium, tungsten, aluminum, cooper, and so on. Metal regions 111, 112, and 113 are then interconnected with various circuit components by metal wiring 114 that is, for simplicity, shown in the drawing only schematically.
To prevent parasitic surface channel conduction and shorting together of plugs 106, 107 and 108, p+ type doped isolation regions (channel stops) 109 are inserted between each of plugs 106, 107 and 108. Typically, channel stops 109 completely surround each of corresponding plugs 106, 107 and 108 in the direction that is perpendicular to the plane of drawing, which is not visible in FIG. 1.
One example of a typical circuit that can be used for detecting charge in the particular n+ type diffusion node is shown as a schematic in FIG. 1. The circuit consists of reset transistor 117 that connects charge detection node 115 to reference voltage terminal 119 when a suitable reset level is applied to gate 118. Photo-generated charge accumulating on node 115 causes a voltage charge that is buffered by transistor 116 with its drain connected to Vdd bias terminal 120. The output signal then appears on node 121 and can be further processed either as a voltage or as a current when supplied to the rest of the sensor circuitry. Circuit ground 122 is identical to p+ type doped substrate 101. For a single pixel that senses three colors, each color has a circuit including reset transistor 117 and amplifier transistor 116, connected as shown in FIG. 1. It would be apparent to those skilled in the art that other, more complex circuits can be connected to pixel 100.
When a reset voltage is applied to node 115 and the corresponding two remaining nodes (circuits connected to plugs 106 and 107, not shown), the potential of these nodes is raised to the reference bias level Vrf. When the doping level of layer 103 (as well as layers 104 and 105) is sufficiently high, the potential at node 115, the potential of plug 108 (as well as plugs 107 and 106), and the potential of layer 103 (as well as layers 104 and 105) are approximately the same. Layer 103 and plug 108, which are buried reverse biased diodes, act as a single electrode of a junction capacitor. The capacitance of such a structure is higher relative to the desired capacitance of pixel 100, since the junction area surrounding layer 103 on all sides is large. Combined with the input gate capacitance of the circuit connected to the node 115, the charge conversion factor of the node is small. As a result, the pixel has low sensitivity, which is undesirable in a sensor. What is needed is a vertically structured pixel with reduced capacitance.